By Stamatis Vassiliadis, Dimitrios Soudris, Y. Patt, J. Smith, M. Valero
The elemental innovations and development blocks for the layout of good- (or FPGA) and Coarse-Grain Reconfigurable Architectures are mentioned during this booklet. Recently-developed built-in structure layout and software-supported layout movement of FPGA and coarse-grain reconfigurable structure also are defined. The publication is followed by way of an interactive CD along with case reviews and lab initiatives for the layout of FPGA and Coarse-grain architectures.
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Additional resources for Fine- and Coarse-Grain Reconfigurable Computing
Tatas et al. 1 provides the main features for some of the above described fine-grain reconfigurable architectures in terms of their programmability, the reconfiguration method, the interface and the possible application domain. 1 Xilinx In this subsection the Spartan-3, Virtex-4 and Virtex-5 families of FPGAs will be described. Besides the fine-grain resources and hard IP blocks (DSP, embedded processors) integrated in many Xilinx devices, a library of soft IP blocks are also available for the efficient implementation of complex systems.
The basic Virtex-4 building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of previous designs. Virtex-4 devices are produced on a 90 nm copper process, using 300 mm (12 inch) wafer technology. Configurable Logic Blocks (CLBs) A CLB resource is made up of four slices. Each slice is equivalent and contains: • • • • • • Two function generators (F & G) Two storage elements Arithmetic logic gates Large multiplexers Fast carry look-ahead chain Horizontal cascade chain The function generators F & G are configurable as 4-input look-up tables (LUTs).
21 Stratix II Adaptive Logic Module (ALM) Local interconnect Local interconnect Local interconnect Local interconnect Local interconnect Local interconnect Local interconnect Local interconnect Shared_arith_in VDD sclr Row, column & Direct link routing CLR Q Row, column & Direct link routing CLR Q Local interconnect Row, column & Direct link routing D SETQ Local interconnect Row, column & Direct link routing D SETQ asyncload ena[1:0] clk[2:0] Reg_chain-out aclr[1:0] syncload Reg_chain-in 1 A Survey of Existing Fine-Grain Reconfigurable Architectures and CAD tools 41 42 K.