VLSI Physical Design: From Graph Partitioning to Timing by Igor L. Markov, Andrew B. Kahng, Jens Lienig, Jin Hu

By Igor L. Markov, Andrew B. Kahng, Jens Lienig, Jin Hu

Layout and optimization of built-in circuits are necessary to the construction of recent semiconductor chips, and actual optimizations have gotten extra widespread because of semiconductor scaling. sleek chip layout has turn into so complicated that it's mostly played by way of really good software program, that's usually up to date to handle advances in semiconductor applied sciences and elevated challenge complexities. A consumer of such software program wishes a high-level realizing of the underlying mathematical types and algorithms. nevertheless, a developer of such software program should have a willing figuring out of machine technological know-how features, together with algorithmic functionality bottlenecks and the way a variety of algorithms function and engage. VLSI actual layout: From Graph Partitioning to Timing Closure introduces and compares algorithms which are used in the course of the actual layout part of integrated-circuit layout, in which a geometrical chip structure is produced ranging from an summary circuit layout. The emphasis is on crucial and primary ideas, starting from hypergraph partitioning and circuit placement to timing closure.

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Order = Ø 6. foreach (node v  V) 7. status[v] = FREE 8. D[v] = COST(v) 9. IS_FIXED(V)) 10. ('gi,(ai,bi)) = MAX_GAIN(A,B) 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. // arbitrary initial partition // set every node as free // compute D(v) for each node // while all cells are not fixed, select free // node ai from A and free node bi from // B so that 'gi = D(ai) + D(bi) – 2c(ai,bi) // is maximized ADD(order,('gi,(ai,bi))) // keep track of swapped cells TRY_SWAP(ai,bi,A,B) // move ai to B, and move bi to A status[ai] = FIXED // mark ai as fixed status[bi] = FIXED // mark bi as fixed foreach (free node vf connected to ai and bi) D[vf] = COST(vf) // compute and update D(vf) i=i+1 (Gm,m) = BEST_MOVES(order) // swap sequence 1 … m that // maximizes Gm if (Gm > 0) CONFIRM_MOVES(order,m) // execute move sequence First, partition the input graph G into two arbitrary partitions A and B (line 1), and set the maximum positive gain value Gm to ’ (line 2).

TRY_MOVE(cell,A,B) 16. else 17. TRY_MOVE(cell,B,A) 18. status[cell] = FIXED 19. foreach (net net  critical_nets) 20. foreach (cell c  net, c  cell) 21. if (status[c] == FREE) 22. UPDATE_GAIN(ǻg[i][c]) 23. i=i+1 24. (Gm, m ) = BEST_MOVES(order) 25. 26. if (Gm > 0) CONFIRM_MOVES(order,m ) // compute balance criterion // initial partition // for each cell, compute the // gain for current iteration, // and set each cell as free // while there are free cells, find // the cell with maximum gain // keep track of cells moved // critical nets connected to cell // if cell belongs to partition A, // move cell from A to B // otherwise, if cell belongs to B, // move cell from B to A // mark cell as fixed // update gains for critical cells // move sequence c1 … cm that // maximizes Gm // execute move sequence First, compute the balance criterion (line 1) and partition the graph (line 2).

1). Each partition must also meet all design constraints. For example, the amount of logic in a partition can be limited by the size of an FPGA chip. , by the number of I/O pins in the chip package. 1 The empirical observation known as Rent’s rule suggests a power-law relationship between the number of cells nG and the number of external connections nP = t˜ nG r, for any subcircuit of a “welldesigned” system. Here, t is the number of pins per cell and r, referred to as the Rent’s exponent or the Rent parameter, is a constant < 1.

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